kind = isa_test
size = 255
immutable_isa = true
title = (31337_35331465118106, `Overture`)
modify_component_budget = [com_level_input_switched: 8, com_level_output_switched: 8]
test_assembly_component = "Program"
tests = 64
optional = true
test_instruction_count = [23658, 24999, 23502, 24982, 24985, 18125, 21937, 24330, 24999, 24209, 24995, 24962, 22277, 23094, 22442, 24992, 24977, 24991, 16785, 21815, 23325, 21403, 24986, 19772, 15895, 24607, 25000, 23093, 24988, 23730, 23775, 24982, 24983, 25000, 18533, 24990, 24990, 22914, 24978, 22323, 24987, 24988, 24998, 24982, 24988, 24996, 24979, 24990, 24979, 23354, 22336, 24978, 22190, 17726, 25000, 24991, 24988, 24994, 21731, 24560, 24993, 24363, 17954, 24997]
dialogue = [
  (mentor_centered, (31337_59797408403606, `The only purpose of this optional level is to let you experiment with how much you can optimize Overture. Unlike previous levels, this level does not require you to complete exactly one instruction per cycle.
  `)),
  (mentor_centered, (31337_59818810946218, `By default, this level only checks that you write the correct values to output. You may opt in to having your register state checked as well, which is very useful for debugging, but this is optional. To have your register state be checked, send the number of instructions you finished each cycle to the component labeled "DoneCount".`))
  (mentor_centered, (31337_84590049728141, `Note that if you change the RAM type to DRAM, you can set the pipeline depth of the RAM. If you for example set the depth to 2, loads and stores will take two cycles, but the delay of the RAM will be divided by 3.`))
]
